1. Field of the Invention
The present invention is related to a dual-loop phase lock loop, and particularly to a dual-loop phase lock loop that can generate a coarse control voltage and a fine control voltage to adjust a feedback clock of the dual-loop phase lock loop according to currents from different current sources.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a dual-loop phase lock loop 100 according to the prior art. The dual-loop phase lock loop 100 utilizes a coarse tune loop with a large gain to adjust an oscillator frequency shift varied with a process, a voltage, and a temperature, and a fine tune loop with a small gain to adjust performance parameters of the dual-loop phase lock loop 100, such as phase noise, random jitter, and loop bandwidth. Therefore, compared to a single-loop phase lock loop, the dual-loop phase lock loop 100 has lower phase noise and random jitter.
However, as shown in FIG. 1, in the dual-loop phase lock loop 100, a capacitor C2 is large for providing a stable zero. In addition, the coarse tune loop and the fine tune loop of the dual-loop phase lock loop 100 have different control voltages, respectively, and the dual-loop phase lock loop 100 has a very complex filter. Therefore, it is difficult to overcome the above mentioned disadvantages for a designer.